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TS4975
Stereo Headphone Drive Amplifier with Digital Volume Control via I2C Bus

Operating from VCC = 2.5V to 5.5V IC bus control interface 40mW output power @ Vcc=3.3V, THD=1%, F=1kHz, with 16 load Ultra-low consumption in stdby mode: 0.6 A Digital volume control range from 18dB to -34dB 14-step digital volume control 9 different output mode selections Pop & click noise reduction circuitry Flip-chip package 12 x 300m bumps (leadfree) Pin Out (top view)
OUT1 PHG1 PHG2 OUT2
TS4975EIJT - Flip Chip

Description
The TS4975 is a stereo audio headphone driver capable of delivering up to 102mW per channel of continuous average power into a 16 singleended load with 1% THD+N from a 5V power supply. The overall gain of these headphone drivers is controlled digitally by volume control registers programmed via the IC interface, minimizing the number of external components needed. This device can also easily be driven by an MCU to select the output modes, through the IC bus interface. A phantom ground configuration allows one to avoid using bulky capacitors on the outputs of the headphone amplifiers. The TS4975 is packaged into a 1.8mm X 2.3mm Flip Chip package, ideally suited for spaceconscious portable applications.
IN1
VCC
GND
IN2
BYPASS
SCL
SDA
ADD
It has also an internal thermal shutdown protection mechanism.
Applications

Mobile phones (cellular / cordless) PDAs Laptop/notebook computers Portable audio devices
Order Codes
Part Number TS4975EIJT Temperature Range -40, +85C Package Flip-chip Packaging Tape & Reel Marking A75
July 2005
Rev 2 1/33
www.st.com 33
Absolute Maximum Ratings
TS4975
1
Absolute Maximum Ratings
Table 1.
Symbol VCC Vi Toper Tstg Tj Rthja Pd ESD ESD Latch-up
Key parameters and their absolute maximum ratings
Parameter Supply voltage (1) Input Voltage (2) Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Thermal Resistance Junction to Ambient (3) Power Dissipation Susceptibility - Human Body Model(5) Susceptibility - Machine Model (min. Value) Latch-up Immunity Lead Temperature (soldering, 10sec) Value 6 GND to VCC -40 to + 85 -65 to +150 150 200 Internally Limited(4) 2 200 200 260 kV V mA C Unit V V C C C C/W
1. All voltages values are measured with respect to the ground pin. 2. The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V 3. Device is protected in case of over temperature by a thermal shutdown active @ 150C. 4. Exceeding the power derating curves during a long period, may involve abnormal operating condition. 5. Human body model, 100pF discharged through a 1.5kOhm resistor, into pin to Vcc device.
Table 2.
Symbol VCC RL CL TOP RTHJA
Operating conditions
Parameter Supply Voltage Load Resistor Load Capacitor RL = 16 to 100, RL > 100, Operating Free Air Temperature Range Flip Chip Thermal resistance Junction to Ambient Value 2.5 to 5.5v >16 400 100 -40 to +85 90 Unit V pF C C/W
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TS4975
Typical Application Schematics
2
Typical Application Schematics
Figure 1 shows typical application schematics for the TS4975 in single-ended output configuration and in phantom ground output configuration. Figure 1. Typical application schematics for two possible configurations Single-ended output configuration
Vcc +
Cb 1F
+
Cs 1F
A1
Bias
IN1 Pre-Amplifier OUT1 Amplifier
Vcc
Bypass
B2
IN1
Cin1
A2
Cout1
RL = 16/32 Ohms
IN1
OUT1
A3
+
+
1k
330nF
PHG1 Amplifier
220F
PHG1 Mode Select
PHG2 Amplifier
B3
PHG2
C3
IN2 Pre-Amplifier
OUT2 Amplifier
IN2
Cin2
D2
Cout2
RL = 16/32 Ohms
IN2
OUT2
D3
+
+
1k
330nF
220F
Volume control
GND ADD
I2C
SDA SCL
TS4975
D1
B1
C2
ADD SCL SDA
Phantom ground output configuration
Vcc
+
Cb 1F
+
Cs 1F
A1
Bypass
Bias
IN1 Pre-Amplifier OUT1 Amplifier
Vcc
B2
C1
RL = 16/32 Ohms
A3
IN1
Cin1
A2
IN1
OUT1
+
330nF
PHG1 Amplifier
PHG1 Mode Select
PHG2 Amplifier
B3
PHG2
C3
IN2 Pre-Amplifier
OUT2 Amplifier
RL = 16/32 Ohms
D3
IN2
Cin2
D2
IN2
OUT2
330nF
+
Volume control
GND ADD
I2C
SCL SDA
TS4975
C2
B1
D1
ADD SCL SDA
C1
3/33
Electrical Characteristics
TS4975
3
Electrical Characteristics
Table 3.
Symbol VIL VIH FSCL Vol Ii
Electrical characteristics for the IC interface
Parameter Maximum Low level Input Voltage on pin SDA, SCL, VADD Minimum High Level Input Voltage on pin SDA, SCL, VADD SCL Maximum clock Frequency Max Low Level Output Voltage, SDA pin, Isink = 3mA Input current on SDA, SCL. From 0.1Vcc to 0.9Vcc Value 0.3 VCC 0.7 VCC 400 0.4 10 Unit V V kHz V A
Table 4.
Output noise (all inputs grounded)
Unweighted Filter from Vcc=2.5V to 5V Weighted Filter (A) from Vcc=2.5V to 5V 23Vrms 45Vrms 23Vrms 45Vrms
SE, G=+2dB SE, G=+18dB PHG, G=+2dB PHG, G=+18dB
34Vrms 67Vrms 34Vrms 67Vrms
4/33
TS4975
Table 5.
Symbol
Electrical Characteristics
VCC = +2.5 V, GND = 0V, Tamb = 25C (unless otherwise specified)
Parameter Supply Current No input signal, no load, Single Ended, Mode 1-4 No input signal, no load, Single Ended, Mode 5-8 No input signal, no load, Phantom Ground, Mode 1-4 No input signal, no load, Phantom Ground, Mode 5-8 Standby Current (SCL and SDA at VCC level) No input signal Output Offset Voltage No input signal, RL = 32, Phantom Ground Output Power THD+N = 1% Max, f = 1kHz, RL = 16, Single Ended THD+N = 1% Max, f = 1kHz, RL = 32, Single Ended THD+N = 1% Max, f = 1kHz, RL = 16, Phantom Ground THD+N = 1% Max, f = 1kHz, RL = 32, Phantom Ground Total Harmonic Distortion + Noise, Av = 2dB RL=32, Po=10 mW, 20Hz < F < 20kHz, Single Ended RL=16, Po=15 mW, 20Hz < F < 20kHz, Single Ended RL=32, Po=10 mW, 20Hz < F < 20kHz, Phantom Ground RL=16, Po=15 mW, 20Hz < F < 20kHz, Phantom Ground Power Supply Rejection Ratio(1) F = 217Hz, RL = 16, Av = 2 dB Vripple = 200mVpp, Input Grounded, Cb = 1F, Single Ended Output referenced to Phantom Ground F = 217Hz, RL = 16, Av = 2 dB Vripple = 200mVpp, Input Grounded, Cb = 1F, Single Ended Output referenced to Ground Channel Separation, RL = 32, Av = 2 dB with Single Ended F = 1kHZ, Po=10mW F = 20Hz to 20kHz, Po=10mW Channel Separation, RL = 32, Av = 2 dB with Phantom Ground F = 1kHZ, Po=10mW F = 20Hz to 20kHz, Po=10mW Signal To Noise Ratio, A-Weighted, Av=2dB, RL=32, Po=12mW Single Ended Phantom Ground Output Noise voltage, A-Weighted, Av=2dB Single Ended Phantom Ground Digital Gain Range In1 & In2 to Out1 & Out2 Digital Gain Stepsize Gain error tolerance -1 25.5 30 110 1 -34 4 +1 34.5 180 15 11 15 11 Min. Typ. 3 2 4.6 3.6 0.6 5 Max. 4.2 2.8 6.5 5.3 2 50 Unit
ICC
mA
ISTANDBY Voo
A mV
Po
21 13 21 13 0.3 0.3 0.3 0.3
mW
THD + N
%
PSRR
60
dB
60 103 75 69 69
Crosstalk
dB
SNR
88 88 23 23 +18
dB
ONoise G
Vrms dB dB dB k ms s
Zin Twu Tws
In1 & In2 Input Impedance, All Gain setting Wake up time, Cb=1F Standby time
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ F = 217Hz
5/33
Electrical Characteristics
Table 6.
Symbol
TS4975
VCC = +3.3V, GND = 0V, Tamb = 25C (unless otherwise specified)
Parameter Supply Current No input signal, no load, Single Ended, Mode 1-4 No input signal, no load, Single Ended, Mode 5-8 No input signal, no load, Phantom Ground, Mode 1-4 No input signal, no load, Phantom Ground, Mode 5-8 Standby Current (SCL and SDA at VCC level) No input signal Output Offset Voltage No input signal, RL = 32, Phantom Ground Output Power THD+N = 1% Max, f = 1kHz, RL = 16, Single Ended THD+N = 1% Max, f = 1kHz, RL = 32, Single Ended THD+N = 1% Max, f = 1kHz, RL = 16, Phantom Ground THD+N = 1% Max, f = 1kHz, RL = 32, Phantom Ground Total Harmonic Distortion + Noise, Av = 2dB RL=32, Po=20 mW, 20Hz < F < 20kHz, Single Ended RL=16, Po=30 mW, 20Hz < F < 20kHz, Single Ended RL=32, Po=20 mW, 20Hz < F < 20kHz, Phantom Ground RL=16, Po=30 mW, 20Hz < F < 20kHz, Phantom Ground Power Supply Rejection Ratio(1) F = 217Hz, RL = 16, Av = 2 dB Vripple = 200mVpp, Input Grounded, Cb = 1F, Single Ended Output referenced to Phantom Ground F = 217Hz, RL = 16, Av = 2 dB Vripple = 200mVpp, Input Grounded, Cb = 1F, Single Ended Output referenced to Ground 34 24 34 24 Min. Typ. 3 2 4.6 3.6 0.6 5 Max. 4.2 2.8 6.5 5.3 2 50 Unit
ICC
mA
ISTANDBY Voo
A mV
Po
40 26 40 26 0.3 0.3 0.3 0.3
mW
THD + N
%
PSRR
61
dB
61 103 75 69 69
Channel Separation, RL = 32, Av = 2 dB with Single Ended F = 1kHZ, Po=20mW F = 20Hz to 20kHz, Po=20mW Crosstalk Channel Separation, RL = 32, Av = 2 dB with Phantom Ground F = 1kHZ, Po=20mW F = 20Hz to 20kHz, Po=20mW Signal To Noise Ratio, A-Weighted, Av=2dB, RL=32, Po=25mW Single Ended Phantom Ground Output Noise voltage, A-Weighted, Av=2dB Single Ended Phantom Ground Digital Gain Range In1 & In2 to Out1 & Out2 Digital Gain Stepsize Gain error tolerance Zin Twu Tws In1 & In2 Input Impedance, All Gain setting Wake up time, Cb=1F Standby time -1 25.5 -34
dB
SNR
90 90 23 23 +18 4 +1 30 90 1 34.5 156
dB
Noise G
Vrms dB dB dB k ms s
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ F = 217Hz
6/33
TS4975
Table 7.
Symbol
Electrical Characteristics
VCC = +5V, GND = 0V, Tamb = 25C (unless otherwise specified)
Parameter Supply Current No input signal, no load, Single Ended, Mode 1-4 No input signal, no load, Single Ended, Mode 5-8 No input signal, no load, Phantom Ground, Mode 1-4 No input signal, no load, Phantom Ground, Mode 5-8 Standby Current (SCL and SDA at VCC level) No input signal Output Offset Voltage No input signal, RL = 32, Phantom Ground Output Power THD+N = 1% Max, f = 1kHz, RL = 16, Single Ended THD+N = 1% Max, f = 1kHz, RL = 32, Single Ended THD+N = 1% Max, f = 1kHz, RL = 16, Phantom Ground THD+N = 1% Max, f = 1kHz, RL = 32, Phantom Ground Total Harmonic Distortion + Noise, Av = 2dB RL=32, Po=50 mW, 20Hz < F < 20kHz, Single Ended RL=16, Po=80 mW, 20Hz < F < 20kHz, Single Ended RL=32, Po=50 mW, 20Hz < F < 20kHz, Phantom Ground RL=16, Po=80 mW, 20Hz < F < 20kHz, Phantom Ground Power Supply Rejection Ratio(1) F = 217Hz, RL = 16, Av = 2 dB Vripple = 200mVpp, Input Grounded, Cb = 1F, Single Ended Output referenced to Phantom Ground F = 217Hz, RL = 16, Av = 2 dB Vripple = 200mVpp, Input Grounded, Cb = 1F, Single Ended Output referenced to Ground Channel Separation, RL = 32, Av = 2 dB with Single Ended F = 1kHZ, Po=50mW F = 20Hz to 20kHz, Po=50mW Channel Separation, RL = 32, Av = 2 dB with Phantom Ground F = 1kHZ, Po=50mW F = 20Hz to 20kHz, Po=50mW Signal To Noise Ratio, A-Weighted, Av=2dB, RL=32, Po=62mW Single Ended Phantom Ground Output Noise voltage, A-Weighted, Av=2dB Single Ended Phantom Ground Digital Gain Range In1 & In2 to Out1 & Out2 Digital Gain Stepsize Gain error tolerance -1 25.5 30 80 1 -34 4 +1 34.5 144 92 59 92 59 Min. Typ. 3 2 4.6 3.6 0.6 5 Max. 4.2 2.8 6.5 5.3 2 50 Unit
ICC
mA
ISTANDBY Voo
A mV
Po
102 64 98 63 0.3 0.3 0.3 0.3
mW
THD + N
%
PSRR
63
dB
63 103 75 69 69
Crosstalk
dB
SNR
95 95 23 23 +18
dB
ONoise G
Vrms dB dB dB k ms s
Zin Twu Tws
In1 & In2 Input Impedance, All Gain setting Wake up time, Cb=1F Standby time
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ F = 217Hz
7/33
Electrical Characteristics
Figure 2. THD+N versus output power Figure 3. THD+N versus output power
TS4975
10
RL = 8 Out. mode 1 - 8 SE, G = +2dB 1 BW < 125kHz Tamb = 25C
10 Vcc=2.5V F=20kHz Vcc=2.5V F=1kHz RL = 8 Out. mode 1 - 8 SE, G = +18dB 1 BW < 125kHz Tamb = 25C THD + N (%)
Vcc=3.3V F=20kHz Vcc=2.5V F=20kHz
THD + N (%)
0.1
0.1 Vcc=3.3V F=1kHz Vcc=2.5V F=1kHz Vcc=5V F=20kHz 0.01 Output power (W)
0.01
Vcc=3.3V F=1kHz
Vcc=3.3V F=20kHz
Vcc=5V F=20kHz
Vcc=5V F=1kHz
0.01
Vcc=5V F=1kHz
1E-3 1E-3
0.01 Output power (W)
0.1
1E-3 1E-3
0.1
Figure 4.
THD+N versus output power
Figure 5.
THD+N versus output power
10 RL = 16 Out. mode 1 - 8 SE, G = +2dB 1 BW < 125kHz Tamb = 25C THD + N (%) Vcc=2.5V F=20kHz Vcc=2.5V F=1kHz
10 RL = 16 Out. mode 1 - 8 SE, G = +18dB 1 BW < 125kHz Tamb = 25C THD + N (%) Vcc=3.3V F=20kHz Vcc=2.5V F=1kHz
0.1
0.1
0.01
Vcc=3.3V F=1kHz
Vcc=3.3V F=20kHz
Vcc=5V F=20kHz
Vcc=5V F=1kHz
0.01
Vcc=2.5V F=20kHz
Vcc=3.3V F=1kHz
Vcc=5V F=20kHz
Vcc=5V F=1kHz
1E-3 1E-3
0.01 Output power (W)
0.1
1E-3 1E-3
0.01 Output power (W)
0.1
Figure 6.
THD+N versus output power
Figure 7.
THD+N versus output power
10 RL = 32 Out. mode 1 - 8 SE, G = +2dB 1 BW < 125kHz Tamb = 25C THD + N (%) Vcc=2.5V F=20kHz
10 RL = 32 Out. mode 1 - 8 SE, G = +18dB 1 BW < 125kHz Tamb = 25C THD + N (%) Vcc=2.5V F=20kHz
0.1 Vcc=5V F=20kHz Vcc=3.3V F=20kHz Vcc=3.3V F=1kHz 0.01 Output power (W) Vcc=5V F=1kHz 0.1
0.1 Vcc=5V F=20kHz Vcc=2.5V F=1kHz Vcc=3.3V F=20kHz 0.01 Output power (W) Vcc=3.3V F=1kHz Vcc=5V F=1kHz 0.1
0.01
Vcc=2.5V F=1kHz
0.01
1E-3 1E-3
1E-3 1E-3
8/33
TS4975
Figure 8. THD+N versus output power Figure 9.
Electrical Characteristics
THD+N versus output power
10 RL = 8 Out. mode 1 - 8 PHG, G = +2dB 1 BW < 125kHz Tamb = 25C THD + N (%) Vcc=2.5V F=20kHz Vcc=2.5V F=1kHz THD + N (%)
10 Vcc=2.5V F=1kHz 1 Vcc=2.5V F=20kHz Vcc=3.3V F=20kHz
0.1
0.1 Vcc=3.3V F=1kHz Vcc=5V F=20kHz 0.01 Output power (W)
0.01
Vcc=3.3V F=1kHz
Vcc=3.3V F=20kHz
Vcc=5V F=20kHz
Vcc=5V F=1kHz
1E-3 1E-3
0.01 Output power (W)
0.1
RL = 8 0.01 Out. mode 1 - 8 SE, G = +18dB BW < 125kHz Tamb = 25C 1E-3 1E-3
Vcc=5V F=1kHz
0.1
Figure 10. THD+N versus output power
Figure 11. THD+N versus output power
10 RL = 16 Out. mode 1 - 8 PHG, G = +2dB 1 BW < 125kHz Tamb = 25C THD + N (%) Vcc=2.5V F=20kHz
10 Vcc=3.3V F=20kHz 1 THD + N (%) Vcc=2.5V F=1kHz Vcc=2.5V F=1kHz Vcc=2.5V F=20kHz
0.1
0.1 Vcc=3.3V F=1kHz Vcc=5V F=20kHz 0.01 Output power (W)
0.01
Vcc=3.3V F=1kHz
Vcc=3.3V F=20kHz
Vcc=5V F=20kHz
Vcc=5V F=1kHz
0.01
RL = 16 Out. mode 1 - 8 PHG, G = +18dB BW < 125kHz Tamb = 25C
Vcc=5V F=1kHz
1E-3 1E-3
0.01 Output power (W)
0.1
1E-3 1E-3
0.1
Figure 12. THD+N versus output power
Figure 13. THD+N versus output power
10 RL = 32 Out. mode 1 - 8 PHG, G = +2dB 1 BW < 125kHz Tamb = 25C THD + N (%) Vcc=2.5V F=20kHz
10 RL = 32 Out. mode 1 - 8 PHG, G = +18dB BW < 125kHz Tamb = 25C Vcc=2.5V F=20kHz
1 THD + N (%)
0.1 Vcc=5V F=20kHz Vcc=2.5V F=1kHz Vcc=3.3V F=20kHz 0.01 Output power (W) Vcc=3.3V F=1kHz Vcc=5V F=1kHz 0.1
0.1 Vcc=5V F=20kHz Vcc=3.3V F=20kHz Vcc=3.3V F=1kHz 0.01 Output power (W) Vcc=5V F=1kHz 0.1
0.01
Vcc=2.5V 0.01 F=1kHz
1E-3 1E-3
1E-3 1E-3
9/33
Electrical Characteristics
Figure 14. THD+N versus frequency Figure 15. THD+N versus frequency
TS4975
10 RL = 8 Output mode 1 - 8 Single Ended G = +2dB 1 BW < 125kHz Tamb = 25C Vcc=2.5V P=20mW 0.1 Vcc=3.3V P=40mW Vcc=5V P=110mW
10 RL = 8 Output mode 1 - 8 Single Ended G = +18dB 1 BW < 125kHz Tamb = 25C Vcc=2.5V P=20mW 0.1 Vcc=3.3V P=40mW Vcc=5V P=110mW
THD + N (%)
0.01
THD + N (%)
100
1000 Frequency (Hz)
10000
0.01
100
1000 Frequency (Hz)
10000
Figure 16. THD+N versus frequency
Figure 17. THD+N versus frequency
10 RL = 16 Output mode 1 - 8 Single Ended G = +2dB BW < 125kHz Tamb = 25C Vcc=2.5V P=15mW 0.1 Vcc=3.3V P=30mW Vcc=5V P=80mW
10 RL = 16 Output mode 1 - 8 Single Ended G = +18dB BW < 125kHz Tamb = 25C Vcc=2.5V P=15mW 0.1 Vcc=3.3V P=30mW Vcc=5V P=80mW
THD + N (%)
0.01
THD + N (%)
1
1
100
1000 Frequency (Hz)
10000
0.01
100
1000 Frequency (Hz)
10000
Figure 18. THD+N versus frequency
Figure 19. THD+N versus frequency
10 RL = 32 Output mode 1 - 8 Single Ended G = +2dB BW < 125kHz Tamb = 25C Vcc=2.5V P=10mW 0.1 Vcc=3.3V P=20mW Vcc=5V P=50mW
10 RL = 32 Output mode 1 - 8 Single Ended G = +18dB BW < 125kHz Tamb = 25C Vcc=2.5V P=10mW 0.1 Vcc=3.3V P=20mW Vcc=5V P=50mW
THD + N (%)
0.01
THD + N (%)
1
1
100
1000 Frequency (Hz)
10000
0.01
100
1000 Frequency (Hz)
10000
10/33
TS4975
Figure 20. THD+N versus frequency
Electrical Characteristics
Figure 21. THD+N versus frequency
10 RL = 8 Output mode 1 - 8 Phantom Ground G = +2dB 1 BW < 125kHz Tamb = 25C Vcc=2.5V P=20mW 0.1 Vcc=3.3V P=40mW Vcc=5V P=110mW
10 RL = 8 Output mode 1 - 8 Phantom Ground G = +18dB 1 BW < 125kHz Tamb = 25C Vcc=2.5V P=20mW 0.1 Vcc=3.3V P=40mW
THD + N (%)
THD + N (%)
Vcc=5V P=110mW 0.01 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000
Figure 22. THD+N versus frequency
Figure 23. THD+N versus frequency
10 RL = 16 Output mode 1 - 8 Phantom Ground G = +2dB BW < 125kHz Tamb = 25C Vcc=2.5V P=15mW 0.1 Vcc=3.3V P=30mW Vcc=5V P=80mW
10 RL = 16 Output mode 1 - 8 Phantom Ground G = +18dB BW < 125kHz Tamb = 25C Vcc=2.5V P=15mW 0.1 Vcc=3.3V P=30mW
THD + N (%)
THD + N (%)
1
1
Vcc=5V P=80mW
0.01
100
1000 Frequency (Hz)
10000
0.01
100
1000 Frequency (Hz)
10000
Figure 24. THD+N versus frequency
Figure 25. THD+N versus frequency
10 RL = 32 Output mode 1 - 8 Phantom Ground G = +2dB BW < 125kHz Tamb = 25C Vcc=2.5V P=10mW 0.1 Vcc=3.3V P=20mW Vcc=5V P=50mW
10 RL = 32 Output mode 1 - 8 Phantom Ground G = +18dB BW < 125kHz Tamb = 25C Vcc=2.5V P=10mW Vcc=3.3V P=20mW Vcc=5V P=50mW
THD + N (%)
THD + N (%)
1
1
0.1
0.01
100
1000 Frequency (Hz)
10000
0.01
100
1000 Frequency (Hz)
10000
11/33
Electrical Characteristics
TS4975
Figure 26. Output power versus power supply Figure 27. Output power versus power supply voltage voltage
180 Output power at 10% THD + N (mW) Output power at 1% THD + N (mW) F = 1kHz 160 Output mode 1 - 8 Single Ended 140 BW < 125 kHz 120 Tamb = 25C 100 80 60 40 20 0 2.5 3.0 3.5 4.0 Vcc (V) 4.5 5.0 64 5.5 32 8 16
220 F = 1kHz Output mode 1 - 8 180 Single Ended 160 BW < 125 kHz Tamb = 25C 140 200 120 100 80 60 40 20 0 2.5 3.0 3.5 4.0 Vcc (V) 4.5 64 5.0 5.5 32 8
16
Figure 28. Output power versus power supply Figure 29. Output power versus power supply voltage voltage
180 Output power at 1% THD + N (mW) Output power at 10% THD + N (mW) 160 140 120 100 80 60 40 20 0 2.5 3.0 3.5 4.0 Vcc (V) 4.5 5.0 64 5.5 F = 1kHz Output mode 1 - 8 Phantom Ground BW < 125 kHz Tamb = 25C 32 8 16
220 F = 1kHz Output mode 1 - 8 180 Phantom Ground 160 BW < 125 kHz Tamb = 25C 140 200 120 100 80 60 40 20 0 2.5 3.0 3.5 4.0 Vcc (V) 4.5 64 5.0 5.5 32 8
16
12/33
TS4975
Figure 30. PSSR versus frequency
Electrical Characteristics
Figure 31. PSSR versus frequency
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 20 G=-2dB 100 1000 Frequency (Hz) 10000 G=-10dB G=-34dB G=+10dB G=+2dB Vcc = 2.5V RL 16 Output mode 1 - 8 SE, Inp. grounded Vripple = 200mVpp
0 -10 -20 G=+18dB PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 20 100 G=-2dB G=-10dB 1000 Frequency (Hz) G=-34dB 10000 G=+10dB Vcc = 2.5V RL 16 Output mode 1 - 8 PHG, Inp. grounded Vripple = 200mVpp
G=+18dB G=+2dB
Figure 32. PSSR versus frequency
Figure 33. PSSR versus frequency
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 20 G=-2dB 100 1000 Frequency (Hz) G=-10dB G=-34dB 10000 G=+10dB G=+2dB Vcc = 3.3V RL 16 Output mode 1 - 8 SE, Inp. grounded Vripple = 200mVpp
0 -10 -20 G=+18dB PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 20 100 G=-2dB G=-10dB 1000 Frequency (Hz) G=-34dB 10000 Vcc = 3.3V RL 16 Output mode 1 - 8 PHG, Inp. grounded Vripple = 200mVpp
G=+18dB
G=+10dB G=+2dB
Figure 34. PSSR versus frequency
Figure 35. PSSR versus frequency
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 20 100 G=-10dB G=-2dB 1000 Frequency (Hz) G=-34dB 10000 G=+10dB G=+2dB Vcc = 5V RL 16 Output mode 1 - 8 SE, Inp. grounded Vripple = 200mVpp
0 -10 -20 G=+18dB PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 20 100 G=-2dB G=-10dB 1000 Frequency (Hz) G=-34dB 10000 G=+10dB G=+2dB Vcc = 5V RL 16 Output mode 1 - 8 PHG, Inp. grounded Vripple = 200mVpp
G=+18dB
13/33
Electrical Characteristics
Figure 36. Crosstalk versus frequency Figure 37. Crosstalk versus frequency
TS4975
Crosstalk Level (dB)
Crosstalk Level (dB)
Vcc = 2.5V Output mode 1 -20 Single Ended G = +2dB -40 Tamb = 25C -60 -80 -100 -120 RL=32 Po=10mW RL=16 Po=15mW
0
0 -10 -20 -30 -40 -50 -60 -70
Vcc = 2.5V Output mode 1 Phantom Ground G = +2dB Tamb = 25C
RL=32 Po=10mW
RL=16 Po=15mW
100
1000 Frequency (Hz)
10000
-80
100
1000 Frequency (Hz)
10000
Figure 38. Crosstalk versus frequency
Figure 39. Crosstalk versus frequency
Crosstalk Level (dB)
Crosstalk Level (dB)
Vcc = 3.3V Output mode 1 -20 Single Ended G = +2dB -40 Tamb = 25C -60 -80 -100 -120 RL=32 Po=20mW RL=16 Po=30mW
0
0 -10 -20 -30 -40 -50 -60 -70
Vcc = 3.3V Output mode 1 Phantom Ground G = +2dB Tamb = 25C
RL=32 Po=20mW
RL=16 Po=30mW
100
1000 Frequency (Hz)
10000
-80
100
1000 Frequency (Hz)
10000
Figure 40. Crosstalk versus frequency
Figure 41. Crosstalk versus frequency
Crosstalk Level (dB)
Crosstalk Level (dB)
Vcc = 5V Output mode 1 -20 Single Ended G = +2dB -40 Tamb = 25C -60 -80 -100 -120 RL=32 Po=50mW RL=16 Po=80mW
0
0 -10 -20 -30 -40 -50 -60 -70
Vcc = 5V Output mode 1 Phantom Ground G = +2dB Tamb = 25C
RL=32 Po=50mW
RL=16 Po=80mW
100
1000 Frequency (Hz)
10000
-80
100
1000 Frequency (Hz)
10000
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TS4975
Figure 42. SNR versus power supply voltage
Electrical Characteristics
Figure 43. SNR versus power supply voltage
110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80
SNR (dB)
2.5
3.3 Vcc (V)
5
SNR (dB)
RL = 32 RL = 16 Out. mode 1 - 8 SE, G = +2dB Unweighted filter (20Hz to 20kHz) THD+N < 0.5% Tamb = 25C
110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80
RL = 32 RL = 16 Out. mode 1 - 8 SE, G = +2dB Weighted filter type A THD+N < 0.5% Tamb = 25C
2.5
3.3 Vcc (V)
5
Figure 44. SNR versus power supply voltage
Figure 45. SNR versus power supply voltage
110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70
SNR (dB)
2.5
3.3 Vcc (V)
5
SNR (dB)
RL = 32 RL = 16 Out. mode 1 - 8 SE, G = +18dB Unweighted filter (20Hz to 20kHz) THD+N < 0.5% Tamb = 25C
110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70
RL = 32 RL = 16 Out. mode 1 - 8 SE, G = +18dB Weighted filter type A THD+N < 0.5% Tamb = 25C
2.5
3.3 Vcc (V)
5
Figure 46. SNR versus power supply voltage
Figure 47. SNR versus power supply voltage
110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80
SNR (dB)
2.5
3.3 Vcc (V)
5
SNR (dB)
RL = 32 RL = 16 Out. mode 1 - 8 PHG, G = +2dB Unweighted filter (20Hz to 20kHz) THD+N < 0.5% Tamb = 25C
110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80
RL = 32 RL = 16 Out. mode 1 - 8 PHG, G = +2dB Weighted filter type A THD+N < 0.5% Tamb = 25C
2.5
3.3 Vcc (V)
5
15/33
Electrical Characteristics
Figure 48. SNR versus power supply voltage
110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70
TS4975
Figure 49. SNR versus power supply voltage
110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70
SNR (dB)
2.5
3.3 Vcc (V)
5
SNR (dB)
RL = 32 RL = 16 Out. mode 1 - 8 PHG, G = +18dB Unweighted filter (20Hz to 20kHz) THD+N < 0.5% Tamb = 25C
RL = 32 RL = 16 Out. mode 1 - 8 PHG, G = +18dB Weighted filter type A THD+N < 0.5% Tamb = 25C
2.5
3.3 Vcc (V)
5
Figure 50. Frequency response
Figure 51. Current consumption versus power supply voltage
6 5
20 18 16 14 Output level (dB) 12 10 8 6 4 2 0 20 100 1000 Frequency (Hz) 10000 Vcc = 5V, 3.3V, 2.5V G = +2dB Vcc = 5V, 3.3V, 2.5V G = +18dB
No loads Tamb = 25C
PHG, Out. Mode 1, 2, 3, 4
Output mode 1 - 8 RL = 32, 16 Cin = 330nF SE, PHG BW < 125kHz Tamb = 25C
4 Icc (mA) 3 2 1 Reset state
PHG, Out. mode 5, 6, 7, 8
SE, Out. mode 1, 2, 3, 4 SE, Out. mode 5, 6, 7, 8 0 0 1 2 3 Vcc (V) 4 5
Figure 52. 3dB lower cut off frequency versus Figure 53. 3dB lower cut off frequency versus input capacitance output capacitance
100 Low -3dB Cut Off Frequency (Hz)
All gain setting Tamb=25C Low -3 dB Cut Off frequency (Hz)
100
All gain setting Tamb = 25C
Minimum Input Impedance Typical Input Impedance Maximum Input Impedance 0.1 Input Capacitor Cin (F) 1
10 RL=16
10
RL=32
1 100
1000 Output capacitor Cout (F)
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TS4975
Figure 54. Power dissipation versus output power (one channel
Electrical Characteristics
Figure 55. Power dissipation versus output power (one channel
70
Vcc = 2.5V F = 1kHz 60 THD+N < 1% Power Dissipation (mW) 50 40 30 20 RL=32, SE 10 0
Power Dissipation (mW)
120
Vcc = 3.3V 110 F = 1kHz 100 THD+N < 1% 90 80 70 60 50 40 30 20 10 0 RL=32, SE RL=16, SE RL=16, PHG RL=32, PHG
RL=16, PHG RL=32, PHG
RL=16, SE
0
5
10
15
20
25
0
5
10
15
20
25
30
35
40
45
Output Power (mW)
Output Power (mW)
Figure 56. Power dissipation versus output power (one channel
Figure 57. Power derating curves
280 Vcc = 5V 260 F = 1kHz 240 THD+N < 1% 220 200 180 160 140 120 100 80 60 40 20 0 0 10 20 30
Flip-Chip Package Power Dissipation (W)
1.4 1.2 1.0 0.8 0.6 0.4 No Heat sink 0.2 0.0 Heat sink surface = 125mm
2
Power Dissipation (mW)
RL=16, PHG RL=32, PHG
RL=16, SE
RL=32, SE
40
50
60
70
80
90 100 110
0
25
Output Power (mW)
50 75 100 Ambiant Temperature (C)
125
150
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Application Information
TS4975
4
Application Information
The TS4975 integrates 2 monolithic power amplifiers. The amplifier output can be configured as either SE (single-ended) capacitively-coupled output or PHG (phantom ground) output. Figure 1 on page 3 shows schemas of these two configurations. In a SE configuration an output capacitor, Cout, on each output is needed. This output coupling capacitor blocks the Vcc/2 voltage (to which the output amplifier is biased) and couples the audio signal to the load. In a PHG configuration, internal buffers are connected to PHG1 and PHG2 pins biased to the Vcc/2 voltage, and output amplifiers are also biased to the Vcc/2 voltage. Therefore, no output capacitors are needed. The advantage of the PHG configuration is fewer external components compared with a SE configuration. However, note that the device has higher power dissipation (see Power dissipation and efficiency on page 22). This chapter gives information on how to configure the TS4975 in application.
4.1
IC bus interface
Table 8 summarizes the pin descriptions for the IC bus interface. Table 8.
Pin SDA SCL ADD
IC bus interface pin descriptions
Functional Description This is the serial data input pin This is the clock input pin User-setable portion of device's I2C address
4.1.1
IC bus operation
The TS4975 uses a serial bus, which conforms to the IC protocol, to control the chip's functions with two wires: Clock and Data. The Clock line is uni-directional. The Data line is bidirectional (open-collector) with an external chip pull-up resistor (typically 10 kOhm). The maximum clock frequency specified by the IC standard is 400kHz. Table 9.
A6 1
Device slave address
A5 1 A4 0 A3 0 A2 1 A1 1 A0 A0 Rw X
The host MCU can write into the TS4975 control registers and read from the control registers. The slave address of the TS4975 for writing is CC or CE hex. In order to write data into the TS4975, after the "start" message, the MCU must send the following data:

send the IC address slave byte with a low level for the R/W bit send the data
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TS4975
Application Information
Figure 58. IC write operation
SLAVE ADDRESS CONTROL REGISTERS
SDA
S
1
1
0
0
1
1 A0
0
A
D7 D6 D5 D4 D3 D2 D1 D0 A
P
Start condition
Volume Control settings
Output Mode settings
Stop condition Acknowledge from Slave
R/W Acknowledge from Slave
Phantom Ground settings
All bytes are sent with MSB bit first. The transfer of written data ends with a "stop" message. When transmitting several data, the data can be written with no need to repeat the "start" message and slave address. The slave address of the TS4975 for reading is CD or CF hex. In order to read data from the TS4975, after the "start" message, the MCU must send and receive the following data:

send the IC address slave byte with a high level for the R/W bit receive the data (control register value)
All bytes are read with MSB bit first. The transfer of read data is ended with "stop" message. When transmitting several data, the data can be read with no need to repeat the "start" message and slave address. In this case the value of control register is read repeatedly. When thermo shutdown or pop and click reduction is active, specific value is read from the TS4975 (See 4: Application Information on page 18). Table 10. Ouput mode selection: G from -34 dB to + 18dB (by steps of 4dB)(1)
Headphone Output 1 SD G x In1 G x In2 G x In1 G x In2 SD SD G x In1 G x In2 Headphone Output 2 SD G x In2 G x In1 G x In1 G x In2 G x In1 G x In2 SD SD
Output Mode # 0 1 2 3 4 5 6 7 8
1. SD = Shutdown Mode In1 = Audio Input 1 In2= Audio Input2 G = Gain from Audio Input 1and Input 2 to Output1 and Output2
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Application Information
TS4975
4.1.2
Gain Register Operation
The gain of the TS4975 ranges from -34dB to +18 dB. At Power-up, both the right and left channels are set in Stand-by mode. Table 11. Gain settings truth table
D7 (MSB) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 D6 0 0 0 1 1 1 1 0 0 0 0 1 1 1 D5 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D4 1 0 1 0 1 0 1 0 1 0 1 0 1 0
G: Gain (dB) # -34 -30 -26 -22 -18 -14 -10 -6 -2 +2 +6 +10 +14 +18
Table 12.
Output mode settings truth table
D2 X x 0 0 0 0 1 1 1 1 D1 X x 0 0 1 1 0 0 1 1 D0 X x 0 1 0 1 0 1 0 1 COMMENTS PHG off PHG on MODE 1 MODE 2 MODE 3 MODE4 MODE 5 MODE 6 MODE 7 MODE 8
D3: PHG on / off 0 1 x X X X X X X X
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TS4975
Table 13.
D7 (MSB) 0
Application Information
Stand-by mode IC condition
D6 0 D5 0 D4 0 D3 X D2 X D1 X D0 X
Table 14.
D7 (MSB) 1
IC control byte states
D6 1 D5 1 D4 1 D3 x D2 X D1 X D0 X Undefined State
4.1.3
Acknowledge
The number of data bytes transferred between the start and the stop conditions from the CPU master to the TS4975 slave is not limited. Each byte of eight bits is followed by one acknowledge bit. The TS4975 which is addressed, generates an acknowledge after the reception of each byte that has been clocked out.
21/33
Application Information
TS4975
4.2
Power dissipation and efficiency
Hypotheses:

Voltage and current in the load are sinusoidal (Vout and Iout). Supply voltage is a pure DC source (Vcc).
VOUT = V PEAK sin t ( V )
Regarding the load we have:
and
V OUT I OUT = -------------- ( A ) RL V PEAK P OUT = ----------------- ( A ) 2RL
2
and
Single-ended configuration:
The average current delivered by the supply voltage is:
V PEAK 1 V PEAK Icc AVG = ------ ----------------- sin ( t ) dt = ---------------- ( A ) RL R L 2
0
Figure 59. Current delivered by supply voltage in single-ended model
The power delivered by supply voltage is:
Psupply = V CC ICC
AVG
(W)
So, the power dissipation by each amplifier is
P diss = P supply - P OUT ( W ) 2V CC P diss = ------------------ P OUT - POUT ( W ) RL
and the maximum value is obtained when:
Pdiss =0 P OUT
22/33
TS4975
and its value is:
P diss
MAX
Application Information
V CC = ------------ ( W ) 2 RL
2
Note:
This maximum value depends only on power supply voltage and load values. The efficiency is the ratio between the output power and the power supply:
V PEAK P OUT = ------------------ = -------------------Psupply 2VCC
The maximum theoretical value is reached when Vpeak = Vcc/2, so
= -- = 78.5% 4
Phantom ground configuration:
The average current delivered by the supply voltage is:
Icc AVG 2V PEAK 1 V PEAK = -- ----------------- sin ( t ) dt = -------------------- ( A ) RL R L
0
Figure 60. Current delivered by supply voltage in phantom ground mode
The power delivered by supply voltage is:
Psupply = V CC ICC
AVG
(W)
Then, the power dissipation by each amplifier is
2 2V CC P diss = ---------------------- P OUT - POUT ( W ) RL
and the maximum value is obtained when:
Pdiss =0 P OUT
and its value is:
P diss
MAX
2V CC = -------------- ( W ) 2 RL
2
Note:
This maximum value depends only on power supply voltage and load values.
23/33
Application Information
The efficiency is the ratio between the output power and the power supply:
P OUT V PEAK = ------------------ = -------------------Psupply 4VCC
TS4975
The maximum theoretical value is reached when Vpeak = Vcc/2, so
= -- = 39.25% 8
The TS4975 is stereo amplifier so it has two independent power amplifiers. Each amplifier produces heat due to its power dissipation. Therefore the maximum die temperature is the sum of each amplifier's maximum power dissipation. It is calculated as follows:

Pdiss 1 = Power dissipation due to the first channel power amplifier. Pdiss 2 = Power dissipation due to the second channel power amplifier. Total Pdiss = Pdiss 1 + Pdiss 2 (W)
In most cases, Pdiss 1 = Pdiss 2, giving:
TotalPdiss = 2Pdiss1
Single ended configuration:
2 2V CC TotalPdiss = ---------------------- P OUT - 2P OUT ( W ) RL
Phantom ground configuration:
4 2V CC TotalPdiss = ---------------------- P OUT - 2P OUT ( W ) RL
4.3
Low frequency response
Input capacitor Cin
The input coupling capacitor blocks the DC part of the input signal at the amplifier input. In the low-frequency region, Cin starts to have an effect. Cin with Zin forms a first-order, high-pass filter with -3 dB cut-off frequency.
1 F CL = ----------------------- ( Hz ) 2Zin C in
Zin is the input impedance of the corresponding input (30 k for In1 & In2). Note: For all inputs, the impedance value remains for all gain settings. This means that the lower cutoff frequency doesn't change with gain setting. Note also that 30 k is a typical value and there is tolerance around this value (see 3: Electrical Characteristics on page 4). In Figure 50 you could easily establish the Cin value for a -3dB cut-off frequency required.
24/33
TS4975
Application Information
Output capacitor Cout
In single-ended mode the external output coupling capacitors Cout are needed. This coupling capacitor Cout with the output load RL also forms a first-order high-pass filter with -3 dB cut off frequency.
1 FCL = ------------------------- ( Hz ) 2R L C out
See Figure 51 to establish the Cout value for a -3dB cut-off frequency required. These two first-order filters form a second-order high-pass filter. The -3 dB cut-off frequency of these two filters should be the same, so the following formula should be respected:
1 1 ----------------------- ------------------------2Z in C in 2R L C out
4.4
Decoupling of the circuit
Two capacitors are needed to properly bypass the TS4975 -- a power supply capacitor Cs and a bias voltage bypass capacitor Cb. Cs has a strong influence on the THD+N in high frequency (above 7kHz) and indirectly on the power supply disturbances. With 1 F, you could expect similar THD+N performances like shown in the datasheet. If Cs is lower than 1 F, THD+N increases in high frequency and disturbances on power supply rail are less filtered. To the contrary, if Cs is higher than 1 F, those disturbances an the power supply rail are more filtered. Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with input grounded in lower frequency:

If Cb is lower than 1 F, THD+N increases at lower frequencies and the PSRR worsens upwards. If Cb is higher than 1 F, the benefit on THD+N and PSRR in the lower frequency range is small.
The value of Cb also has an influence on startup time.
4.5
Power-on reset
When power is applied to Vdd, an internal Power On Reset holds the TS4975 in a reset state until the supply voltage reaches its nominal value. The Power On Reset has a typical threshold of 1.75V.
25/33
Application Information
TS4975
4.6
Notes on PSRR measurement
What is PSRR?
The PSRR is the Power Supply Rejection Ratio. The PSRR of a device is the ratio between a power supply disturbance and the result on the output. In other words, the PSRR is the ability of a device to minimize the impact of power supply disturbance to the output.
How we measure the PSRR?
The PSRR was measured according to the schematic shown in Figure 61. Figure 61. PSRR measurement schematic
Principles of operation

The DC voltage supply (Vcc) is fixed The AC sinusoidal ripple voltage (Vripple) is fixed No bypasss capacitor Cs is used
The PSRR value for each frequency is calculated as:
RMS ( Output PSRR = 20Log ---------------------------------) ( dB ) RMS ( Vripple )
RMS is a rms selective measurement.
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TS4975
Application Information
4.7
Startup time
When the TS4975 is controlled to switch to full standby (output mode 0) to another output mode, a delay is necessary to stabilize the DC bias.This length of this delay depends on the Cb and Vcc values. A typical value can be calculated by following formula:
V CC t wu = C b x ------------------------ x 50000 + 0.008 ( s ) V CC - 1.2
This formula assumes that Cb voltage is equal to 0 V. If the Cb voltage is not equal 0 V, the startup time will be always lower. In Figure 50 you could easily establish typical startup time for given supply voltage and bypass capacitor Cb. Figure 62. Typical startup time versus bypass capacitance
400 350 300 Startup time (ms) 250 200 150 100 50 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Vcc=5V Vcc=3.3V Vcc=2.5V
Bypass capacitor Cb (F)
4.8
Pop and click performance
The TS4975 has internal pop and click reduction circuitry which eliminates the output transients, for example during switch-on or switch-off phases, during a switch from an output mode to another or during change in volume. The performance of this circuitry is closely linked to the values of the input capacitor Cin, the output capacitor Cout (for Single-Ended configuration) and the bias voltage bypass capacitor Cb. The value of Cin and Cout is determined by the the lower cut-off frequency value requested. The value of Cb will affect the THD+N and PSRR values in lower frequencies. The TS4975 is optimized to have a low pop and click in the typical schematic configuration ( see Figure 1 on page 3 SE and PHG configurations).
27/33
Application Information
TS4975
During the device start-up period when the pop and click reduction is active, the value FX hex (1111xxxx bin) can be read from the internal device registry. Once the device is fully operational and the pop and click is inactive, the last value of control register can be read.
4.9
Thermo shutdown
The TS4975 device has internal protection in case of over temperature by thermal shutdown. Thermal shutdown is active when the device reaches temperature 150C. When thermo shutdown protection is active, value FX hex (1111xxxx bin) can be read from the internal device registry. When thermo shutdown protection state disappears, the last value of control register can be read.
4.10
Demoboard
A demoboard for the TS4975 is available. For more information about this demoboard, please refer to Application Note AN2151, which can be found on www.st.com. Figure 60 shows the schematic of the demoboard. Figure 61, Figure 62 and Figure 64 show the component locations, top layer and bottom layer respectively.
28/33
TS4975
Figure 63. Demoboard schematic
Vcc1 Vcc1
Application Information
Cn1 + C1 1F + C2 1F
14
U1 Cn6 R1 1k
2
Bypass
IN1 Pre-Amplifier P1 IN1 + 330nF C10 1
OUT1 Amplifier C3
IN1
OUT1
13
220F JP1 PHG1 Amplifier 1 2 3 4 HEADER 4 PHG2 Amplifier Cn7 1 J1 2 3 PHONEJACK STEREO 10
PHG1 Mode Select
12
1 2 3
+
Bias
Vcc
PHG2
IN2 Pre-Amplifier P2 IN2 + 330nF C11 6
OUT2 Amplifier C4
IN2
OUT2
9
+ 220F
Volume control
GND ADD
I2C
SCL SDA
1 2 3
R2 1k
TS4975
Cn8
8
5
3
Vcc1
4
JP2 R3 10k 4 3 2 1 Cn4 Cn3 HEADER 4 Vcc1 Vcc1
Cn2
1 2 3
R4 10k
R5 10k
I2C BUS
SDA
SCL SDA SDA Vcc2 SCL
SCL
SDA
Vcc1
Vcc2 Vcc2
R6 360R U2B 3 4 Vcc2
14 13
R8 180R U2A 1 CON1 1 6 2 7 3 8 4 9 5 RS232 GND2 2 KP1040
R7 10K Cn5 16 15 GND2
Vcc2 + KP1040
C5 1F
16
GND2 13 8 11 10
GND2 R1IN R2IN T1IN T2IN C1+ C1C2+ C2V+ V-
U3 R1OUT R2OUT T1OUT T2OUT 12 9 14 7
R9 360R U2C 5 6 KP1040
12 11
DTR GND
+ C6 0.1F GND2 C7 0.1F 1 3 4 5 2 6 C9 0.1F +
+
C8 0.1F
+
GND GND2 15 ST232
Vcc2 GND2
Figure 64. Bottom layer
Vcc
TXD
29/33
Application Information
Figure 65. Top layer Figure 66. Componens location
TS4975
30/33
TS4975
Package Mechanical Data
5
Package Mechanical Data
Figure 67. TS4975 Footprint Recommendation
500m =250m 500m 75m min. 100m max. Track
500m
=400m typ. =340m min.
150m min.
Non Solder mask opening Pad in Cu 18m with Flash NiAu (2-6m, 0.2m max.)
Figure 68. Pin out (top view)
3
OUT1 PHG1 PHG2 OUT2
500m
2
IN1
VCC
GND
IN2
1
BYPASS
SCL
SDA
ADD
A
B
C
D
Figure 69. Marking (top view)

Logo: ST Part Number: A75 Date Code: YWW The Dot is for marking pin A1
E
E Lead Free symbol
A75 YW W
31/33
Package Mechanical Data
Figure 70. Flip-chip - 12 bumps
2300m
TS4975
1800m 500m
Die size: 2.3mm x 1.8mm 30m Die height (including bumps): 600m Bumps diameter: 315m 50m Bump diameter before reflew: 300m 10m Bumps height: 250m 40m Die height: 350m 20m

500m
600m
Figure 71. Tape & reel specification (top view)
4
1.5
1 A A
Die size Y + 70m
1
8
Die size X + 70m
4
All dimensions are in mm
User direction of feed
32/33
TS4975
Revision History
6
Revision History
Date November-2004 July 2005 Revision 1 2 Initial release. Product in full production Changes
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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